Patent · US Active

Method of manufacturing and testing a chip package

US9082644B2 · kind B2 · utility

11Cited by

5References

22Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Peter Ossimitz · Munich, DE
Matthias von Daak · Borgo San Lazzaro, DE
Gottfried Beer · Nittendorf, DE

Key dates

Filing date	Jan 18, 2013
Grant date	Jul 14, 2015
Priority date	—
Expiry date	May 27, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2224/48091
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A method of producing and testing a chip package is described. The chip package to be produced includes a semiconductor chip containing an integrated circuit and a reinforcing structure attached to the semiconductor chip. Further, the chip package has a lower main face and an upper main face opposite to the lower main face, wherein the lower main face is at least partly formed by an exposed surface of the semiconductor chip and the upper main face is formed by a terminal surface of the reinforcing structure on which external terminal pads of the chip package are arranged. After production, the package is subjected to a package-level burn-in test.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.