Peter Ossimitz
17Patents
3h-index
16Co-inventors
53Inventor score
Filing activity: Sep 17, 2004 → Feb 1, 2016
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9362187B2 | Chip package having terminal pads of different form factors | Electricity | 42 | Active |
| US9082644B2 | Method of manufacturing and testing a chip package | Electricity | 11 | Active |
| US9204543B2 | Integrated IC package | Emerging Cross-Sectional Technologies | 3 | Active |
| US7640469B2 | Electronic element comprising an electronic circuit which is to be tested and test system arrangement which is used to test the electronic element | Physics | 3 | Expired |
| US9859251B2 | Semiconductor device having a chip under package | Electricity | 2 | Active |
| US7560801B2 | Rewiring substrate strip with several semiconductor component positions | Electricity | 1 | Expired |
| US8779577B2 | Semiconductor chip comprising a plurality of contact pads and a plurality of associated pad cells | Electricity | 1 | Active |
| US9219031B2 | Chip arrangement, and method for forming a chip arrangement | Electricity | 0 | Active |
| US9651630B2 | Circuitry and method for monitoring a power supply of an electronic device | Electricity | 0 | Active |
| US9299673B2 | Method for manufacturing a semiconductor chip with each contact pad having a pad cell associated therewith | Electricity | 0 | Active |
| US7154116B2 | Rewiring substrate strip with a number of semiconductor component positions | Electricity | 0 | Expired |
| US8399265B2 | Device for releasably receiving a semiconductor chip | Electricity | 0 | Active |
| US9385059B2 | Overmolded substrate-chip arrangement with heat sink | Emerging Cross-Sectional Technologies | 0 | Active |
| US9871017B2 | Multi-level chip interconnect | Electricity | 0 | Active |
| US7501701B2 | Rewiring substrate strip having a plurality of semiconductor component positions | Electricity | 0 | Active |
| US8799704B2 | Semiconductor memory component having a diverting circuit | Physics | 0 | Active |
| US10090251B2 | Semiconductor chip having a dense arrangement of contact terminals | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.