IGZO devices with reduced threshhold voltage shift and methods for forming the same
US9082793B1 · kind B1 · utility
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20Claims
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Key dates
| Filing date | Dec 19, 2013 |
| Grant date | Jul 14, 2015 |
| Priority date | — |
| Expiry date | Dec 19, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6757
Abstract
Embodiments described herein provide indium-gallium-zinc oxide (IGZO) devices, such as IGZO thin-film transistors (TFTs), and methods for forming such devices. A substrate is provided. A gate electrode is formed above the substrate. A gate dielectric layer is formed above the gate electrode. An interface layer is formed above the gate dielectric material. An IGZO channel layer is formed above the interface layer. A source electrode and a drain electrode are formed above the IGZO channel layer. The interface layer includes a material different than that of the gate dielectric layer and the IGZO channel layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.