Timing-aware test generation and fault simulation

US9086454B2 · kind B2 · utility

Assignee

• MENTOR GRAPHICS CORPORATION · US

Inventors

• Xijiang Lin · West Linn, US
• Kun-Han Tsai · Lake Oswego, US
• Mark Kassab · Wilsonville, US
• Chen Wang · Tigard, US
• Janusz Rajski · West Linn, US

Key dates

• Filing date: Oct 14, 2013
• Grant date: Jul 21, 2015
• Expiry date: Oct 14, 2033

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F30/20
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.