Reducing pipeline restart penalty
US9086889B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2010 |
| Grant date | Jul 21, 2015 |
| Priority date | — |
| Expiry date | Jul 12, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0855
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed relating to reducing the latency of restarting a pipeline in a processor that implements scouting. In one embodiment, the processor may reduce pipeline restart latency using two instruction fetch units that are configured to fetch and re-fetch instructions in parallel with one another. In some embodiments, the processor may reduce pipeline restart latency by initiating re-fetching instructions in response to determining that a commit operation is to be attempted with respect to one or more deferred instructions. In other embodiments, the processor may reduce pipeline restart latency by initiating re-fetching instructions in response to receiving an indication that a request for a set of data has been received by a cache, where the indication is sent by the cache before determining whether the data is present in the cache or not.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.