System and method to inject a bit error on a bus lane
US9092312B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2012 |
| Grant date | Jul 28, 2015 |
| Priority date | — |
| Expiry date | Jul 10, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/25
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes modifying, at a bit error injection circuit, a multiplier value by a first value according to an occurrence of a first event. The method also includes, in response to a determination that the modified multiplier value matches a first threshold, modifying, at the bit error injection circuit, the offset value according to an occurrence of a second event. The method further includes, in response to a determination that the modified offset value matches a second threshold, asserting, at the bit error injection circuit, an error injection signal. The method further includes asserting a first error pattern to be transmitted via a bus lane based on the error injection signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.