Method and system for achieving die parallelism through block interleaving
US9092340B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2009 |
| Grant date | Jul 28, 2015 |
| Priority date | — |
| Expiry date | Aug 2, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5643
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for achieving die parallelism through block interleaving includes non-volatile memory having a multiple non-volatile memory dies, where each die has a cache storage area and a main storage area. A controller is configured to receive data and write sequentially addressed data to the cache storage area of a first die. The controller, after writing sequentially addressed data to the cache storage area of the first die equal to a block of the main storage area of the first die, writes additional data to a cache storage area of a next die until sequentially addressed data is written into the cache area of the next die equal to a block of the main storage area. The cache storage area may be copied to the main storage area on the first die while the cache storage area is written to on the next die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.