Methods of forming electronic elements with ESD protection

US9093272B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Daniel J. Lamey · Phoenix, US
• David C. Burdeaux · Midland, US
• Olivier Lembeye · Fonsorbes, FR

Key dates

• Filing date: Sep 6, 2013
• Grant date: Jul 28, 2015
• Expiry date: Feb 1, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/83

Abstract

An electrostatic discharge (ESD) protection circuit (40) is coupled across input-output (I/O) pads (21) and common terminals (24) of a circuit core (22) to protect it from ESD events. The circuit (40) comprises, a unidirectional ESD clamp (23) and two or more floating diodes (42, 44) arranged in parallel opposed configuration in series with the ESD clamp (23), the combination coupled between the I/O pads (21) and the reference terminals (24). In a preferred arrangement, the two strings of opposed parallel coupled diodes (42, 44) are used with different numbers of diodes in each string. These diodes (42, 44) operate in forward conduction (43, 45), so the energy dissipated therein during an ESD event is much reduced compared to a reverse biased diode and they can have smaller area. Signal clipping at the I/O pad (21) is reduced, less power is dissipated and less chip area is utilized.