Methods for selectively coating three-dimensional features on a substrate
US9093323B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jul 15, 2013 |
| Grant date | Jul 28, 2015 |
| Priority date | — |
| Expiry date | Jul 15, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldChemical engineering
- WIPO sectorChemistry
Abstract
Methods here disclosed provide for selectively coating three-dimensional features on a substrate while avoiding liquid coating material wicking into micro cavities on the substrates. The steps include depositing a semiconductor layer on a sacrificial layer formed on a template and selectively etching the sacrificial layer. Then, the steps include releasing the semiconductor layer from the template and coating three-dimensional features on the substrate using a liquid coating step for applying a liquid coating material to a pre-determined surface of the three-dimensional features on the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.