Stacked microelectronic packages having patterned sidewall conductors and methods for the fabrication thereof
US9093457B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2012 |
| Grant date | Jul 28, 2015 |
| Priority date | — |
| Expiry date | Aug 22, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging microelectronic device panels in a panel stack. Each microelectronic device panel includes a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are formed in the panel stack exposing the plurality of package edge conductors. An electrically-conductive material is deposited into the trenches and contacts the plurality of package edge conductors exposed therethrough. The panel stack is then separated into partially-completed stacked microelectronic packages. For at least one of the partially-completed stacked microelectronic packages, selected portions of the electrically-conductive material are removed to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.