Semiconductor device manufacturing method
US9099349B2 · kind B2 · utility
8Cited by
2References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2013 |
| Grant date | Aug 4, 2015 |
| Priority date | — |
| Expiry date | Aug 5, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/27
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a process of dividing gates of multi-layered films in fabricating a NAND flash memory having a three-dimensional structure, a pattern is prevented from deforming and falling. A ratio of a length L to a height h of control gate groups configuring a memory cell of the flash memory is set to be less than 1.65 which is a range in which buckling does not occur. It is desirable that a ratio of a length L to a width W of the control gate groups is set to be less than 16.5.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.