Method of fabricating erasable programmable single-poly nonvolatile memory
US9099392B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2013 |
| Grant date | Aug 4, 2015 |
| Priority date | — |
| Expiry date | Oct 7, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method of fabricating an erasable programmable single-poly nonvolatile memory, comprising the steps of: defining a first area and a second area in a first type substrate; forming a second type well region in the first area; forming a first gate oxide layer and a second gate oxide layer covering a surface of the first area, wherein the second gate oxide layer extends to and is adjacent to the second area; forming a DDD region in the second area; etching a portion of the second gate oxide layer above the second area; forming two polysilicon gates covering the first and the second gate oxide layers; and defining a second type doped region in the DDD region and defining first type doped regions in the second type well region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.