Circuit for reverse biasing inverters for reducing the power consumption of an SRAM memory
US9099993B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2012 |
| Grant date | Aug 4, 2015 |
| Priority date | — |
| Expiry date | Oct 18, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
CMOS integrated circuits with very low consumption when idle, and notably the SRAM volatile memories, are provided. The inverters of the circuit are made up of an NMOS transistor and a PMOS transistor. A bias circuit applies a first rear bias voltage NBIAS to the wells of the NMOS transistors and a second rear bias voltage PBIAS to the wells of the PMOS transistors. The bias circuit comprises: a detection array made up of many inverters in parallel, having a common output supplying a logic signal whose value depends on the rear bias voltages applied to the array, a circuit for producing incrementation or decrementation pulses, controlled by the output of the detection array, and an integration circuit linked to the pulse-producing circuit, for producing and varying, progressively by increments in response to these pulses, a bias voltage PBIAS and a bias voltage NBIAS.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.