Flash memory apparatus with serial interface and reset method thereof
US9104401B2 · kind B2 · utility
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3Claims
0Family size
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Key dates
| Filing date | Oct 31, 2014 |
| Grant date | Aug 11, 2015 |
| Priority date | — |
| Expiry date | Oct 31, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory apparatus with serial interface is disclosed. The flash memory apparatus includes a command receiver, a command decoder and a core circuit. The command receiver sequentially receives a plurality of command data through the data input pin and the clock pin. The command decoder receives a command sequence formed by the command data, and compares the command sequence with a reference sequence to generate a reset signal. The core circuit receives the reset signal to activate a reset operation according to the reset signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.