Wear leveling for a memory device
US9104547B2 · kind B2 · utility
4Cited by
1References
38Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 3, 2011 |
| Grant date | Aug 11, 2015 |
| Priority date | — |
| Expiry date | Apr 8, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices and methods to facilitate wear leveling operations in a memory device. In one such method, particular blocks of memory cells are excluded from experiencing wear leveling operations performed on the memory device. In at least one method, a user selects blocks of memory to be excluded from wear leveling operations performed on the remainder of blocks of the memory device. Selected blocks of memory are excluded from wear leveling operations responsive to a command initiated by a user identifying, either directly or indirectly, the selected blocks to be excluded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.