Memory system controller
US9104555B2 · kind B2 · utility
13Cited by
10References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2013 |
| Grant date | Aug 11, 2015 |
| Priority date | — |
| Expiry date | Aug 6, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure includes methods and devices for a memory system controller. In one or more embodiments, a memory system controller includes a host interface communicatively coupled to a system controller. The system controller has a number of memory interfaces, and is configured for controlling a plurality of intelligent storage nodes communicatively coupled to the number of memory interfaces. The system controller includes logic configured to map between physical and logical memory addresses, and logic configured to manage wear level across the plurality of intelligent storage nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.