Identifying and mitigating electromigration failures in signal nets of an integrated circuit chip design
US9104832B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2014 |
| Grant date | Aug 11, 2015 |
| Priority date | — |
| Expiry date | Apr 24, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of characterizing an electromigration (EM) parameter for use in an integrated circuit (IC) chip design including, inputting a layout of a wire layer and identifying a signal gate-circuit including electrically parallel paths, connected to an output of the signal gate from the layout. Based on widths for each of the paths, determining a maximum possible current for each of the paths, and calculating an average current for each of the paths. Identifying a path that is most limited in its current carrying capacity by possible EM failure mechanisms, and storing in a design library, a possible maximum current output to the identified limiting path, as the EM parameter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.