Method of fabricating an interconnection structure in a CMOS comprising a step of forming a dummy electrode
US9105692B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2013 |
| Grant date | Aug 11, 2015 |
| Priority date | — |
| Expiry date | Oct 21, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating an interconnection structure in a complementary metal-oxide-semiconductor (CMOS) includes forming an opening in a dielectric layer over a substrate and forming a dummy electrode in a first portion of the opening in the dielectric layer. The method further includes filling a second portion of the opening with a second work-function metal layer, wherein a top surface of the second work-function metal layer is below a top surface of the opening and removing the dummy electrode. The method further includes depositing a first work-function metal layer in the first and second portions, whereby the first work-function metal layer is over the second work-function metal layer in the opening and depositing a signal metal layer over the first work-function metal layer in the first and second portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.