Reconfigurable circuit and decoder therefor
US9110133B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 2014 |
| Grant date | Aug 18, 2015 |
| Priority date | — |
| Expiry date | May 14, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4902
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A digital decoder, used in a reconfigurable circuit, for decoding digital pulses includes a phase indicator module having inputs coupled to a reference pulse input and a data pulse input. The phase indicator module has timing information outputs that provide logic values indicative of rising and falling edges of pulses occurring on the reference pulse input and the data pulse input. A phase decoder module has inputs coupled to the timing information outputs, and outputs decoded binary data values. In operation, the phase decoder module compares at least two of the logic values at the timing information outputs with a signal representative leading and trailing edges of a pulse applied to one of the phase inputs to determine a pulse arrival order sequence on the phase inputs and thereby provide the decoded binary data values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.