Chip testing with exclusive OR

US9110135B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Steven M. Douskey · Rochester, US
• Mary P. Kusko · Poughkeepsie, US
• Cedric Lichtenau · Stuttgart, DE

Key dates

• Filing date: Sep 23, 2013
• Grant date: Aug 18, 2015
• Expiry date: Oct 17, 2033

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318566
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

First and second scan channels each comprise a plurality of scannable latches that apply input to and receive output from logic circuits on a chip under test. First input is scanned into the first scan channel and second input is scanned into the second scan channel. Output from the first scan channel is hashed using a first XOR on the first scan channel and output from the second scan channel is hashed using a first XOR on the second scan channel. Output from the first XOR on the first scan channel is hashed using a second XOR on the first scan channel. A rotator creates adjustment data from the output from the second XOR on the first scan channel. The adjustment data and output from the first XOR on the second scan channel are hashed using a second XOR on the second scan channel.