Processor and method implemented by a processor to implement mask load and store instructions
US9110802B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2010 |
| Grant date | Aug 18, 2015 |
| Priority date | — |
| Expiry date | Nov 3, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0721
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of implementing a mask load or mask store instruction by a processor is provided. The method may include receiving the mask load or mask store instruction, a location of a memory operand and a location of corresponding mask bits associated with the memory operand, breaking the received memory operand into a plurality of sub-operands and executing the mask load or mask store instruction on each of the plurality of sub-operands using a fastpath operation or using microcode, wherein the respective mask load or mask store instruction loads or stores each of the plurality of sub-operands based upon the corresponding mask bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.