Memory device
US9111599B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 10, 2014 |
| Grant date | Aug 18, 2015 |
| Priority date | — |
| Expiry date | Jun 10, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/025
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device including a training circuit, a data strobe transmission path, data transmission paths, data latching circuits and a phase detection circuit is provided. When the memory device is under a training mode, a training process is performed on at least one of the data transmission paths. The phase detection circuit detects a phase difference between signals between the data transmission path and the data strobe transmission path to adjust a delay time of the adjustable delay circuit of the data transmission path until the signals are in phase. When the memory device is under an operation mode, each of the data latching circuits receives a treed data strobe signal from the data strobe transmission path to latch a delayed data signal received from the adjustable delay circuit of one of the data transmission paths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.