Patent · US Active

Integrated circuits with protected resistors and methods for fabricating the same

US9111756B2 · kind B2 · utility

0Cited by

4References

15Claims

0Family size

Assignee

GlobalFoundries Inc. · KY

Inventors

Joachim Patzer · Rohrbach, DE
Hans-Peter Moll · Dresden, DE

Key dates

Filing date	Sep 23, 2013
Grant date	Aug 18, 2015
Priority date	—
Expiry date	Jan 1, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH10D1/47
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Methods and apparatus are provided for an integrated circuit with a transistor and a resistor. The method includes depositing a first dielectric layer over the transistor and the resistor, followed by an amorphous silicon layer. The amorphous silicon layer is implanted over the resistor to produce an etch mask, and the amorphous silicon layer and first dielectric layer are removed over the transistor. A contact location on the transistor is then silicided.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.