Semiconductor structure with improved channel stack and method for fabrication thereof
US9111785B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2013 |
| Grant date | Aug 18, 2015 |
| Priority date | — |
| Expiry date | Jul 31, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0191
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor structure with a channel stack includes forming a screening layer under a gate of a PMOS transistor element and a NMOS transistor element, forming a threshold voltage control layer on the screening layer, and forming an epitaxial channel layer on the threshold control layer. At least a portion of the epitaxial channel layers for the PMOS transistor element and the NMOS transistor element are formed as a common blanket layer. The screening layer for the PMOS transistor element may include antimony as a dopant material that may be inserted into the structure prior to or after formation of the epitaxial channel layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.