Patent · US Active

Chip arrangement with a recessed chip housing region and a method for manufacturing the same

US9111947B2 · kind B2 · utility

2Cited by

2References

17Claims

0Family size

Assignee

Intel Deutschland GmbH · DE

Inventors

David O'Sullivan · Ottobrunn, DE
Thorsten Meyer · Regensburg, DE

Key dates

Filing date	Jun 4, 2013
Grant date	Aug 18, 2015
Priority date	—
Expiry date	Jun 21, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/19104
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A chip arrangement may include: a semiconductor chip; an encapsulating structure at least partially encapsulating the semiconductor chip, the encapsulating structure having a first side and a second side opposite the first side, the encapsulating structure including a recess over the first side of the encapsulating structure, the recess having a bottom surface located at a first level; and at least one electrical connector disposed at the first side of the encapsulating structure outside the recess, wherein a surface of the at least one electrical connector facing the encapsulating structure may be disposed at a second level different from the first level.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.