Wafer processing utilizing a frame with a plurality of partitions
US9112019B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2014 |
| Grant date | Aug 18, 2015 |
| Priority date | — |
| Expiry date | Nov 21, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer processing method for dividing a wafer into individual devices along a plurality of crossing division lines includes preparing a frame having a plurality of crossing partitions corresponding to the division lines of the wafer, spreading a liquid resin on the front side or back side of the wafer and positioning the partitions of the frame in alignment with the division lines of the wafer, thereby covering with the liquid resin the regions on the front side or back side of the wafer other than the regions corresponding to the division lines, curing the liquid resin supplied to the front side or back side of the wafer and next removing the frame, thereby masking the regions other than the regions corresponding to the division lines, and plasma-etching the wafer processed by the masking to thereby divide the wafer into the individual devices along the division lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.