Epitaxial structure and process thereof for non-planar transistor
US9112030B2 · kind B2 · utility
2Cited by
1References
17Claims
0Family size
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Key dates
| Filing date | Nov 4, 2013 |
| Grant date | Aug 18, 2015 |
| Priority date | — |
| Expiry date | Jan 10, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/83
Abstract
An epitaxial structure for a non-planar transistor is provided. A substrate has a fin-shaped structure. A gate is disposed across the fin-shaped structure. A silicon germanium epitaxial structure is disposed on the fin-shaped structure beside the gate, wherein the silicon germanium epitaxial structure has 4 <1,1,1> surfaces and its aspect ratio of width and thickness is at a range of 1:1˜1.3. A method for forming said epitaxial structure is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.