Voids in STI regions for forming bulk FinFETs
US9112052B2 · kind B2 · utility
8Cited by
14References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 12, 2014 |
| Grant date | Aug 18, 2015 |
| Priority date | — |
| Expiry date | May 12, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment is an integrated circuit structure including two insulation regions over a substrate with one of the two insulation regions including a void, at least a bottom surface of the void being defined by the one of the two insulation regions. The integrated circuit structure further includes a first semiconductor strip between and adjoining the two insulation regions, where the first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions, a gate dielectric over a top surface and sidewalls of the fin, and a gate electrode over the gate dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.