Memory array plane select and methods
US9117503B2 · kind B2 · utility
8Cited by
4References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2012 |
| Grant date | Aug 25, 2015 |
| Priority date | — |
| Expiry date | Jan 3, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/71
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory arrays and methods of forming the same are provided. An example memory array can include at least one plane having a plurality of memory cells arranged in a matrix and a plurality of plane selection devices. Groups of the plurality of memory cells are communicatively coupled to a respective one of a plurality of plane selection devices. A decode logic having elements is formed in a substrate material and communicatively coupled to the plurality of plane selection devices. The plurality of memory cells and the plurality of plane selection devices are not formed in the substrate material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.