Semiconductor device and method of forming non-linear interconnect layer with extended length for joint reliability
US9117812B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2013 |
| Grant date | Aug 25, 2015 |
| Priority date | — |
| Expiry date | Dec 23, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has a substrate and first conductive layer formed over the substrate. An insulating layer is formed over the first substrate with an opening over the first conductive layer. A second conductive layer is formed within the opening of the insulating layer. A portion of the second conductive layer is removed to expose a horizontal surface and side surfaces of the second conductive layer below a surface of the insulating layer. The second conductive layer has non-linear surfaces to extend a contact area of the second conductive layer. The horizontal surface and side surfaces can be stepped surfaces or formed as a ring. A third conductive layer is formed over the second conductive layer. A plurality of bumps is formed over the horizontal surface and side surfaces of the second conductive layer. A semiconductor die is mounted to the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.