Device architecture and method for improved packing of vertical field effect devices
US9117899B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2013 |
| Grant date | Aug 25, 2015 |
| Priority date | — |
| Expiry date | Dec 24, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/519
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor field-effect device is disclosed that utilizes an octagonal or inverse-octagonal deep trench super-junction in combination with an octagonal or inverse-octagonal gate trench. The field-effect device achieves improved packing density, improved current density, and improved on resistance, while at the same time maintaining compatibility with the multiple-of-45°-angles of native photomask processing and having well characterized (010), (100) and (110) (and their equivalent) silicon sidewall surfaces for selective epitaxial refill and gate oxidation, resulting in improved scalability. By varying the relative length of each sidewall surface, devices with differing threshold voltages can be achieved without additional processing steps. Mixing trenches with varying sidewall lengths also allows for stress balancing during selective epitaxial refill.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.