D3 Semiconductor LLC
12Patents
12Active
12Granted
47Portfolio score
Filing activity: Nov 26, 2013 → Mar 5, 2018
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9117899B2 | Device architecture and method for improved packing of vertical field effect devices | Electricity | 3 | Active |
| US9806186B2 | Termination region architecture for vertical power transistors | Electricity | 2 | Active |
| US9755058B2 | Surface devices within a vertical power device | Electricity | 2 | Active |
| US9496386B2 | Device architecture and method for improved packing of vertical field effect devices | Electricity | 1 | Active |
| US10580884B2 | Super junction MOS bipolar transistor having drain gaps | Electricity | 1 | Active |
| US10074735B2 | Surface devices within a vertical power device | Electricity | 1 | Active |
| US9865727B2 | Device architecture and method for improved packing of vertical field effect devices | Electricity | 0 | Active |
| US9589889B2 | Device architecture and method for precision enhancement of vertical semiconductor devices | Electricity | 0 | Active |
| US9997455B2 | Device architecture and method for precision enhancement of vertical semiconductor devices | Electricity | 0 | Active |
| US10134890B2 | Termination region architecture for vertical power transistors | Electricity | 0 | Active |
| US9117709B2 | Device architecture and method for precision enhancement of vertical semiconductor devices | Electricity | 0 | Active |
| US9837358B2 | Source-gate region architecture in a vertical power semiconductor device | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.