Non-planar transistor
US9117909B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2014 |
| Grant date | Aug 25, 2015 |
| Priority date | — |
| Expiry date | Aug 28, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed in the first region and the second region, wherein each two first trenches defines a first fin structure. The first fin structure in the second region is removed. Lastly, the first trenches are deepened to form a plurality of second trenches having a second depth, wherein each two second trenches define a second fin structure. The present invention further provides a structure of a non-planar transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.