Method for forming a strained transistor by stress memorization based on a stressed implantation mask

US9117929B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Frank Wirbeleit · Dresden, DE
• Roman Boschke · Dresden, DE
• Martin Gerhardt · Dresden, DE

Key dates

• Filing date: May 16, 2011
• Grant date: Aug 25, 2015
• Expiry date: Jun 22, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/021
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

By using an implantation mask having a high intrinsic stress, SMT sequences may be provided in which additional lithography steps may be avoided. Consequently, a strain source may be provided without significantly contributing to the overall process complexity.