Patent · US Active

Methods of forming stressed fin channel structures for FinFET semiconductor devices

US9117930B2 · kind B2 · utility

0Cited by
1References
25Claims
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Assignee

Inventors

Key dates

Filing dateAug 6, 2013
Grant dateAug 25, 2015
Priority date
Expiry dateNov 18, 2033

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D84/853

Abstract

One method disclosed herein includes forming a first stressed conductive layer within the trenches of a FinFET device and above the upper surface of a fin, forming a second stressed conductive layer above the first stressed conductive layer, removing a portion of the second stressed conductive layer and a portion of the first stressed conductive layer that is positioned above the fin while leaving portions of the first stressed conductive layer positioned within the trenches, and forming a conductive layer above the second stressed conductive layer, the upper surface of the fin and the portions of the first stressed conductive layer positioned within the trenches.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.