Memory controller for reducing capacitive coupling in a cross-point memory
US9123410B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2013 |
| Grant date | Sep 1, 2015 |
| Priority date | — |
| Expiry date | Aug 27, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/77
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a memory controller. The memory controller may include a memory controller module configured to identify a target word line in response to a memory access request, the target word line included in a cross-point memory, the memory controller module further configured to perform a memory access operation on a memory cell of the cross-point memory, the memory cell coupled between the target word line and a bit line; and a word line control module configured to float at least one adjacent word line adjacent the target word line, the floating comprising decoupling the at least one adjacent word line from at least one of a first voltage source or a second voltage source. In some embodiments, the floating reduces an effective capacitance associated with the target word line during the memory access operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.