Semiconductor device with single-event latch-up prevention circuitry

US9123545B2 · kind B2 · utility

Inventors

• Jianan Yang · Austin, US
• James D. Burnett · Austin, US
• Brad J. Garni · Austin, US
• Thomas W. Liston · Austin, US

Key dates

• Filing date: Feb 24, 2014
• Grant date: Sep 1, 2015
• Expiry date: Feb 24, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/854

Abstract

A semiconductor device includes a parasitic silicon-controlled rectifier (SCR) and a first transistor. The parasitic SCR includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The first transistor is coupled between a first power supply node and an emitter of the parasitic pnp BJT. The first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor is not positioned between a base of the pnp BJT and the first power supply node. The first transistor limits current conducted by the parasitic pnp BJT following a single-event latch-up (SEL) event.