Integrated circuits and methods of forming integrated circuits with interlayer dielectric protection
US9123783B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2012 |
| Grant date | Sep 1, 2015 |
| Priority date | — |
| Expiry date | Feb 13, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76814
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuits and methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a base substrate having an embedded electrical contact disposed therein. An interlayer dielectric is formed overlying the base substrate, and a recess is etched through the interlayer dielectric over the embedded electrical contact. A protecting liner is formed in the recess and over an exposed surface of the embedded electrical contact in the recess. The protecting liner includes at least two liner layers that have materially different etch rates in different etchants. A portion of the protecting liner is removed over the surface of the embedded electrical contact to again expose the surface of the embedded electrical contact in the recess. An embedded electrical interconnect is formed in the recess. The embedded electrical interconnect overlies the protecting liner on sides of the recess.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.