Split gate non-volatile flash memory cell having a silicon-metal floating gate and method of making same
US9123822B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2013 |
| Grant date | Sep 1, 2015 |
| Priority date | — |
| Expiry date | Aug 2, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A non-volatile memory cell includes a substrate of a first conductivity type with first and second spaced apart regions of a second conductivity type, forming a channel region therebetween. A select gate is insulated from and disposed over a first portion of the channel region which is adjacent to the first region. A floating gate is insulated from and disposed over a second portion of the channel region which is adjacent the second region. Metal material is formed in contact with the floating gate. A control gate is insulated from and disposed over the floating gate. An erase gate includes a first portion insulated from and disposed over the second region and is insulated from and disposed laterally adjacent to the floating gate, and a second portion insulated from and laterally adjacent to the control gate and partially extends over and vertically overlaps the floating gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.