On-chip bad block management for NAND flash memory
US9128822B2 · kind B2 · utility
19Cited by
3References
6Claims
0Family size
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Key dates
| Filing date | Jun 22, 2012 |
| Grant date | Sep 8, 2015 |
| Priority date | — |
| Expiry date | Sep 28, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Certain functions relating to creation and use of a look-up table for bad block mapping may be implemented “on chip” in the memory device itself, that is on the same die in an additional circuit, or even within the command and control logic of the memory device, so as to reduce the overhead. Moreover, the on-chip implementation of the look-up table may be tightly integrated with other functions of the command and control logic to enable powerful new commands for NAND flash memory, such as a continuous read command and variations thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.