Programmable memory repair scheme
US9129712B2 · kind B2 · utility
10Cited by
44References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2014 |
| Grant date | Sep 8, 2015 |
| Priority date | — |
| Expiry date | Jan 8, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2229/743
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A controller including a non-volatile memory to store a repair address, and a memory control unit operatively coupled with the non-volatile memory. The memory control unit comprising a memory test function configured to detect a malfunctioning address of primary data storage elements within a memory device. The memory device being another semiconductor device separate from the controller. The memory test function configured to store the repair address in the non-volatile memory, the repair address indicating the malfunctioning address of the primary data storage element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.