Distributed cache coherency directory with failure redundancy
US9135175B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2013 |
| Grant date | Sep 15, 2015 |
| Priority date | — |
| Expiry date | Sep 9, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a number of processors with each processor including a cache memory. The system also includes a number of directory controllers coupled to the processors. Each directory controller may be configured to administer a corresponding cache coherency directory. Each cache coherency directory may be configured to track a corresponding set of memory addresses. Each processor may be configured with information indicating the corresponding set of memory addresses tracked by each cache coherency directory. Directory redundancy operations in such a system may include identifying a failure of one of the cache coherency directories; reassigning the memory address set previously tracked by the failed cache coherency directory among the non-failed cache coherency directories; and reconfiguring each processor with information describing the reassignment of the memory address set among the non-failed cache coherency directories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.