Patent · US Active

Memory controller and method for interleaving DRAM and MRAM accesses

US9135965B2 · kind B2 · utility

2Cited by

4References

21Claims

0Family size

Assignee

Everspin Technologies, Inc. · US

Inventors

Syed M. Alam · Austin, US
Thomas Andre · Austin, US
Dietmar Gogl · South Burlington, US

Key dates

Filing date	Dec 16, 2011
Grant date	Sep 15, 2015
Priority date	—
Expiry date	Mar 3, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG11C2207/2272
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory controller and method for interleaving volatile and non-volatile memory different latencies and page sizes are described wherein a single DDR3 memory controller communicates with a number of memory modules comprising of at least non-volatile memory, e.g., spin torque magnetic random access memory, integrated in a different Rank or Channel with a volatile memory, e.g., dynamic random access memory (DRAM).

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.