Structure and method for E-beam writing
US9136092B2 · kind B2 · utility
0Cited by
8References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2012 |
| Grant date | Sep 15, 2015 |
| Priority date | — |
| Expiry date | Apr 9, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/31764
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a main feature; performing an optical proximity correction (OPC) process to the design layout; and thereafter, performing a jog reduction process to the design layout such that jog features of the design layout are reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.