Method of creating alignment/centering guides for small diameter, high density through-wafer via die stacking
US9136259B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 11, 2008 |
| Grant date | Sep 15, 2015 |
| Priority date | — |
| Expiry date | Jan 17, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49117
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for forming a die stack. The method includes forming a plurality of through-wafer vias and a first plurality of alignment features in a first die. A second plurality of alignment features is formed in a second die, and the first die is stacked on the second die such that the first plurality of alignment features engage the second plurality of alignment features. A method of manufacturing a die stack is also provided that includes forming a plurality of through-wafer vias on a first die, forming a plurality of recesses on a first die, and forming a plurality of protrusions on a second die. A die stack and a system are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.