Semiconductor constructions
US9136331B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2013 |
| Grant date | Sep 15, 2015 |
| Priority date | — |
| Expiry date | Jun 22, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/743
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some embodiments include semiconductor constructions having semiconductor material patterned into two mesas spaced from one another by at least one dummy projection. The dummy projection has a width along a cross-section of X and the mesas have widths along the cross-section of at least 3X. Some embodiments include semiconductor constructions having a memory array region and a peripheral region adjacent the memory array region. Semiconductor material within the peripheral region is patterned into two relatively wide mesas spaced from one another by at least one relatively narrow projection. The relatively narrow projection has a width along a cross-section of X and the relatively wide mesas have widths along the cross-section of at least 3X.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.