Controller and method for using a transaction flag for page protection
US9141308B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2011 |
| Grant date | Sep 22, 2015 |
| Priority date | — |
| Expiry date | Feb 7, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A controller is presented having one or more interfaces through which to communicate with a plurality of memory dies with multi-level memory cells and an interface through which to communicate with a host. The controller also contains a processor that is configured to receive a command from the host to program data in a plurality of lower pages and a plurality of upper pages of the multi-level memory cells. The controller detects an indication from the host that indicates which previously-programmed lower pages from a previous program command are at risk of being corrupted by the programming of the upper pages from the received program command. Prior to programming the upper pages, the controller backs up the previously-programmed lower pages from the previous program command that are at risk of being corrupted but not the lower pages of data programmed by the received program command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.