Method for placing operational cells in a semiconductor device
US9141753B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2011 |
| Grant date | Sep 22, 2015 |
| Priority date | — |
| Expiry date | Dec 12, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY04S40/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is provided a method of placing a plurality of operational cells of a semiconductor device within a semiconductor layout, comprising determining timing data for each of the plurality of operational cells, determining switching activity from RTL or design constraints for each of the plurality of operational cells, determining power grid switch locations relative to each of the plurality of operational cells, deriving a cost function based upon the determined timing data, determined switching activity from RTL/design constraints and determined relative power grid switch locations and initially placing the plurality of operational cells according to the derived cost function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.