System to reduce stress on word line select transistor during erase operation
US9142305B2 · kind B2 · utility
14Cited by
18References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2013 |
| Grant date | Sep 22, 2015 |
| Priority date | — |
| Expiry date | Nov 23, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for erasing a non-volatile storage system that reduces the voltage across the word line select transistors which interface between the word lines and global control lines. The use of the lower voltage across the word line select transistors allows for the word line select transistors to be made smaller. The use of smaller components allows the non-volatile storage system to include more memory cells, thereby providing the ability to store more data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.