Field effect transistor devices with buried well protection regions
US9142668B2 · kind B2 · utility
8Cited by
6References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2013 |
| Grant date | Sep 22, 2015 |
| Priority date | — |
| Expiry date | Mar 13, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/292
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a transistor device includes providing a drift layer having a first conductivity type, forming a first region in the drift layer, the first region having a second conductivity type that is opposite the first conductivity type, forming a body layer on the drift layer including the first region, forming a source layer on the body layer, forming a trench in the source layer and the body layer above the first region and extending into the first region, forming a gate insulator on the inner sidewall of the trench, and forming a gate contact on the gate insulator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.